Current Openings

Chipletz is a funded, early-stage start-up with industry veterans from AMD and other major system providers.  Our vision is to revolutionize semiconductor in-package functionality.  As a fabless supplier of intelligent substrates, Chipletz is positioned to provide the building blocks for the next generation of computing systems for traditional and emerging semiconductor markets. 

Developing great technology takes more than talent: It takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve incredible results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to look at the opportunities available on our team.

SI/PI Engineer

Role

Responsible for the Signal and Power integrity of new products and development vehicles.  Member of an advanced packaging team, focused on developing new technologies for heterogeneous packages. Defines test chip/test vehicle strategy to qualify new technology building blocks. Partners with internal and external organizations to optimize design and analyze performance vs yield trade-off. Drive technology design rules with ecosystem partners and support package design, SI/PI studies on new packaging concepts to drive advanced packaging technologies to support new Chipletz products.  Package and board/system level power delivery network AC and DC simulation for low voltage/high-current supplies, DC/DC power conversion.  Package and board/system level signal simulation of future DDR5, HBM memory bus including silicon I/O, package substrates, RDLs and interposers.  System-level signal integrity simulations of future high-speed SERDES links such as USB-4, PCIe5, xGMI3, etc. including silicon I/O, package substrates, RDLs and interposers.  Electromagnetic modeling of package substrate 3D structure, bump/uBump interface.  Implementation of a HVM solution-space methodology.

The Person

The candidate should have a proven track record in Signal and Power integrity analysis including leading high speed transmission line designs and leading package designers for the development of both products and advanced development vehicles that are pushing the state of the art.  The candidate should have excellent verbal and written communication skills to articulate ideas to technology partners, colleagues, and product architects.   Expect some domestic travel. 

Key Responsibilities 

• State-of-The-Art Package stack up planning for signal, power, ground and embedded allocations. 
• Power distribution network design concepts, optimizing stack up and power/ground plane assignments for minimal voltage noise. 
• Power noise analysis in transient and frequency domain with Die, Package, PCB and Voltage Regulator for decoupling optimization and layout guideline definitions. 
• System-level timing budgeting, length matching, design implementation and layout guidance.  
• Crosstalk analysis and reduction techniques. 
• Simultaneous Switching Noise with I/O power domain, Silicon I/O, Package substrate, RDL and interposer co-simulation for Eye diagram and Jitter analysis. 
• High-speed channel simulation for low Bit-Error-Rate (BER) and Eye-Diagram analysis. 

Minimum Experience 

• 5+ years of experience with B.S. in Engineering or 3+ years of experience with advanced degree
• Solid background on transmission line, electromagnetics and microwave theory with in-depth knowledge in Package and PCB high-speed layout techniques. 
• Solid background on power distribution network, inductor, capacitor and voltage regulator. 
• Detailed understanding of S-parameter, Z-parameter, and Fourier transform (FFT). 
• Familiar with Cadence Allegro layout navigation and electrical constraints. 
• Experience with SI/PI simulation tools such as Synopsys HSPICE, Cadence Spectre, ANSYS HFSS/3D-Layout/Q3D, ANSYS SiWave, KeySight ADS, and/or Seasim. 
• Experience with MSO/DSO, BERT, TDR, VNA, Spectrum Analyzer and Probe Station 
• C/C++/Perl/Python programming 

Preferred Experience 

• Chip power grid knowledge with Redhawk 
• Worked directly with substrate suppliers to optimize materials and process 
• Direct experience with high-speed interfaces 32Gbps or faster 
• In-depth knowledge of I/O buffer IBIS Power-Aware modeling 
• Familiar with equalization techniques such as FIR, CTLE, DFE, FFE and noise categories in the system and channel, and to optimize EQ settings. 
• Familiar with high-speed digital logic RX and TX modeling, and Bit-Error-Rate (BER) theory. 

Location

Austin, TX 

Role 

Responsible for new product package design, verification, and validation.  Member of an advanced packaging team, focused on developing new technologies for heterogeneous packages. Defines test chip/test vehicle strategy to qualify new technology building blocks. Partners with internal and external organizations to optimize design and analyze performance vs yield trade-off. Drive technology design rules with ecosystem partners and support package design, SI/PI studies on new packaging concepts to drive advanced packaging technologies to support new Chipletz products.  

The Person

The candidate should have a proven track record in developing board or package design rules with ecosystem partners as well as hands on experience in test chip and general understanding of substrate design. He/she should be able to leverage a deep expertise in board design or already possess a deep understanding of substrate design to complete the package design tasks.  The candidate should have excellent verbal and written communication skills to articulate ideas to technology partners, colleagues, and product architects.   Expect some domestic travel.

Key Responsibilities 

• Design and develop advanced packaging technologies for Chipletz products
• Define and implement design for manufacturing/design for yield (DFM/DFY) guidelines
• Ability to drive cost and SI/PI assessment based on design
• Test chip, test vehicle design support
•  

Minimum Experience

• Experience with Cadence-APD/Allegro and/or Mentor Graphics-XPD, Autocad
• 5yrs experience with B.S. in Engineering or 4yrs experience with Master of engineering
• Experience with scripting tools such as Python, PERL, SKILL, etc. 

Preferred Experience

• Defining and implementing advanced design rules as well as DFM/DFY rules
• Demonstrated leadership mentoring others
• Working directly with OSATs and substrate vendors  

Location

Austin, TX